The present invention relates to semiconductor devices and to methods of forming the same and, more particularly, to a non-volatile memory device and methods of forming the same.
Non-volatile memory devices continuously hold their stored data even when their power supplies are interrupted. Representative non-volatile memory devices include flash memory devices. For example, a typical flash memory device includes a floating gate and a control gate electrode. As charges are injected/discharged to/from the floating gate, a flash memory device stores data of logic “1” or “0”.
For instance, a split-gate type flash memory device is disclosed in U.S. Pat. No. 5,045,488. This patent purports to disclose a floating gate formed using a thermal oxide to have a curved-up top surface, thereby resulting in a peak being formed on the floating gate. Conventional flash memory devices, such as those discussed in U.S. Pat. No. 5,045,488 will now be described with reference to FIG. 1 through FIG. 3.
As illustrated in FIG. 1, a gate oxide layer 2, a polysilicon layer 3, and a silicon nitride layer 4 are sequentially formed on a semiconductor substrate 1. The silicon nitride layer 4 is patterned to form an opening 5 exposing a predetermined region of the polysilicon layer 3. A pair of openings 5 are symmetrically formed at the silicon nitride layer 4.
The substrate 1 is thermally oxidized to form a thermal oxide layer 6 on the exposed polysilicon layer 3. Since a bird's beak is formed at the edge of the thermal oxide layer 6, the thermal oxide layer 6 becomes thinner toward its edge from its center. The bird's beak extends downwardly toward the silicon nitride layer 4 consisting of a sidewall of the opening 5.
As illustrated in FIG. 2, the silicon nitride layer 4 is removed. Using the thermal oxide layer 6 as a mask, the polysilicon layer 3 and the gate oxide layer 2 are etched anisotropically successively to form a pair of floating gates 3a disposed symmetrically. A peak is formed on the edge of the floating gate 3a due to the thermal oxide layer 6.
An intergate oxide layer 7 and a control gate conductive layer 8 are sequentially formed on a semiconductor substrate 1 including the floating gate 3a. A pair of photoresist patterns 9 are symmetrically formed on the control gate conductive layer 8. The photoresist patterns 9 cover a portion of the floating gate 3a and a portion of the semiconductor substrate 1 adjacent to the floating gate 3a. 
As illustrated in FIG. 3, using the photoresist pattern 9 as a mask, the control gate conductive layer 8 and the intergate oxide layer 7 are anisotropically etched to form a control gate electrode 8a. The control gate electrode 8a covers a peak of the floating gate 3a and a portion of the semiconductor substrate 1 adjacent to one side of the floating gate 3a. 
Following removal of the photoresist pattern 9, impurities are selectively implanted to form first and second impurity doping layers. The first impurity doping layer 10a is formed on the semiconductor substrate 1 between the floating gates 3a, and the second impurity doping layer 10b is formed on the semiconductor substrate 1 adjacent to one side of the floating gate 3a opposite to the first impurity doping layer 10a. 
In the above-described conventional flash memory device, an electric field is concentrated on the peak of the floating gate 3a to reduce an erase voltage for discharging charges stored in the floating gate 3a to the control gate electrode 8a. 
However, in forming conventional flash memory devices, the spaces of openings 5 continue to decrease due to the continuing demand for higher integration density of semiconductor devices. As a result, when floating gates 3a are formed using the thermal oxide layer 6 as a mask, bird's beaks adjacent the thermal oxide layers 6 may penetrate below the silicon nitride layer 4 between the pair of the thermal oxide layers 6 to be interconnected, thereby causing the adjacent floating gates 3a to become interconnected to one another via the thermal oxide layers 6. However, the floating gates 3a must be isolated electrically because otherwise if adjacent floating gates 3a are instead connected to one another, this results in the malfunction of the flash memory device.
Moreover, the thickness of the control gate conductive layer 8 may vary with its formation location due to the floating gate 3a. Particularly, the gap region between the floating gates 3a has become narrower due to the recent trend toward higher integration density of semiconductor devices. Thus, the control gate conductive layer 8 filling a gap region between the floating gates 3a may now become thicker than a control gate conductive layer 8 formed on a planar substrate 1 that is opposite to the gap region. In other words, the control gate conductive layer 8 on the semiconductor substrate 1 where the first impurity doping layer 10a is formed may be thicker than the control gate conductive layer 8 on the semiconductor substrate 1 where the second impurity doping layer 10b is formed. As a result, when an etch process is performed to form the control gate electrode 8a, a surface of the semiconductor substrate 1 where the second impurity doping layer 10b is formed may be more severely damaged than a surface of the semiconductor substrate 1 where the first impurity doping layer 10a is formed. Also, a surface of the semiconductor substrate 1 adjacent to opposite sides of a gate electrode of a peripheral circuit transistor formed in a peripheral circuit using the control gate conductive layer 8 may be damaged severely. Due to surface damage to the substrate 1, a surface of the second impurity doping layer 10b and/or surfaces of source/drain regions may become rough and their junction depth may decrease. Moreover, the above described damage also results in the generation of a leakage current.